Boundary-Scan test

JTAGs praktiske og utprøvede boundary-scan løsninger leverer integrerte test- og programmeringsmetoder gjennom hele livssyklusen for produktet. Dette hjelper utviklingen i form av spart tid og penger i hvert nivå av et produkts livssyklus. Kunder som velger JTAGs markedsledende løsninger sikrer maksimal testdekning, høy ytelse på in-system programmering (ISP), bekymringsfri støtte for multiple scan-lenker, et bredt utvalg av boundary-scan kontrollere med autonom bruk, nøyaktig feilanalyse og diagnose, samt en velkjent historikk av produktforbedringer.

What is Boundary-scan?

Boundary-scan (also known as JTAG boundary-scan) is a method of testing modern Printed Circuit Boards (PCBs) after assembly. Using the dedicated test logic built into many of today’s integrated circuits (ICs), boundary-scan checks if each device is correctly inserted and soldered onto the PCB.

Applications

Typical devices that incorporate boundary-scan technology include CPLDs, FPGAs, microprocessors, DSPs, ASICs, bus logic, SERDES, telecom encoders, PHYs and Bridges (PCI/PCIe).

A number of device manufacturers embracing boundary-scan technology are Intel, Analog Devices, ARM, Freescale, NXP, PLX, ST, TI, Renesas, Xilinx, Altera, Lattice, Broadcom and Actel among others.

In practice

Boundary-scan enabled devices feature four (or sometimes five) dedicated test access port (TAP) signals:

  • TCK (Test Clock)
  • TMS (Test Mode Select)
  • TDI (Test Data In)
  • TDO (Test Data Out)
  • TRST (Test Logic Reset) (optional)


To simplify the test infrastructure within a PCB it is common to connect the devices in a serial (daisy chain) formation so that the first device's TDO connects to the next device’s TDI (and so on) to form a so-called scan chain.

To activate the boundary-scan logic, simply pulse TCK while toggling TMS as specified in the TAP state machine map. Once activated, boundary-scan logic controls the device's pins while isolating the primary core functions of the device.